Nonvolatile semiconductor memory devices where data can be electrically written and written data can be stored in a nonvolatile state have such properties that stored data can be stored without being lost even when the power is turned off, but generally are limited in terms of how many times data can be written, as well as the rate of writing (approximately 10 ms or less), and therefore are not appropriate for applications where data is written frequently. Such nonvolatile semiconductor memory devices include EEPROM's (electrically erasable and programmable read only memories) and flash memories. Meanwhile, volatile semiconductor memory devices where data can be electrically written and written data can be stored in a volatile state lose stored data when the power is turned off, but are not limited in terms of how many times data can be written, and have a very high rate of writing in comparison with nonvolatile semiconductor memory devices (100 ns or less). Typical nonvolatile semiconductor memory devices include DRAM's (dynamic random access memories) and SRAM's (static random access memories).
Thus, nonvolatile random access memories (NVRAM's) where the memory cell structure of the volatile semiconductor memory device and the memory cell structure of the nonvolatile semiconductor memory device are integrated so that it is possible to write data at a high rate, which is a good point in volatile semiconductor memory devices, as well as to store data even when the power is turned off, as in nonvolatile semiconductor memory devices, have been developed (see for example the following Patent Documents 1 and 2).
Patent Document 1 discloses a nonvolatile dynamic random access memory (NVDRAM) having memory cells where a DRAM cell and an EEPROM cell are combined. As shown in the equivalent circuit diagram of FIG. 13, the memory cell disclosed in Patent Document 1 has such a structure that one of the drain and source of the transistor Q11 that becomes a transfer gate of the DRAM cell is connected to a bit line BL, the other is connected to one of the drain and source of the second MIS transistor Q12, the gate of the transistor Q11 is connected to a word line WL, the other of the drain and source of the second MIS transistor Q12 is connected to one of the drain and source of the transistor Q13 for preventing the second MIS transistor Q12 from interfering with the operation of the DRAM, the gate of the second MIS transistor Q12 is connected to a writing control line GL, the other of the drain and source of the transistor Q13 is connected to a control line SL, the gate of the transistor Q13 is connected to a switching control line TL, one end of a capacitor element Cs is connected to the connection point between the other of the drain and source of the transistor Q11 and one of the drain and source of the second MIS transistor Q12, and the other end is grounded.
Patent Document 2 discloses a nonvolatile static random access memory (NVSRAM) having memory cells where an SRAM cell and an EEPROM cell are combined. As shown in the equivalent circuit diagram of FIG. 14, the memory cell disclosed in Patent Document 2 has such a structure that EEPROM cells Q20 and Q21 are connected to a pair of complementary data storage nodes DN and DNB in a resistive load SRAM cell, respectively, via selection transistors Q22 and Q23.
Next, nonvolatile semiconductor memory devices that can be mounted on a substrate during a standard CMOS process include the nonvolatile semiconductor memory device disclosed in the following Patent Document 3. The structure of the nonvolatile semiconductor memory device disclosed in Patent Document 1 is described below in reference to FIG. 15. FIG. 15A is a schematic cross sectional diagram showing a memory cell used in the nonvolatile semiconductor memory device in Patent Document 1, and FIG. 15B is an equivalent circuit diagram thereof.
In the memory cell 100 in FIG. 15A, an N type well 102 is formed on a P type semiconductor substrate 101 and P type impurity diffusion layers 110 and 111, as well as an N+ type impurity diffusion layer 112, are formed on the well 102. In addition, the P type impurity diffusion layer 111 and the N+ type impurity diffusion layer 112 are isolated from each other by an element isolation insulating film 114. In addition, separate N type impurity diffusion layers 108 and 109 are formed within the region on the semiconductor substrate 101 where there is no N type well 102 (hereinafter referred to as “region outside well”). In addition, the N type impurity diffusion layer 109 and the P type impurity diffusion layer 110 formed on the N type well 102 are isolated from each other by an element isolation insulating film 113.
Thus, a first gate electrode 106 is formed through a first gate insulating film 104 over the region outside the well so as to overlap with the region between the N type impurity diffusion layers 108 and 109. Meanwhile, a second gate electrode 105 is formed through a second gate insulating film 103 over the N type well 102 region so as to overlap with the region between the P type impurity diffusion layers 110 and 111. Here, the first gate electrode 106 and the second gate electrode 105 are electrically connected through a conductor 107.
In addition, the memory cell 100 is provided with a contact C101 for electrical connection to the N type impurity diffusion layer 108, a contact C102 for electrical connection to the N type impurity diffusion layer 109, and a contact C103 for collective electrical connection to the P type impurity diffusion layers 110 and 111 and the N+ type impurity diffusion layer 112. As shown in FIG. 15A, the P type impurity diffusion layers 110 and 111 and the N+ type impurity diffusion layer 112 are all connected to the same node, so that the structure allows the same voltage to be applied to all of the impurity diffusion layers 110, 111 and 112 when a predetermined voltage is applied to the contact C103.
The nonvolatile semiconductor memory device disclosed in Patent Document 3 is formed of a memory cell array where a number of memory cells 100 having the above described structure are aligned in rows and columns. At this time, memory cells having a predetermined positional relationship are electrically connected to each other through the same bit line, word line or source line. In the following, the contact C101, the contact C102 and the contact C103 are connected to a bit line, a source line and a word line, respectively.
The memory cell 100 in FIG. 15A is provided with a MOS transistor Q30 formed of the P type semiconductor substrate 101, the N type impurity diffusion layer 108, the N type impurity diffusion layer 109, the first gate insulating film 104 and the first gate electrode 106, and a MOS capacitor Q31 formed of the N type well 102, the P type impurity diffusion layer 110, the P type impurity diffusion layer 111, the second gate insulating film 103 and the second gate electrode 105. In addition, the first gate electrode 106 that forms the MOS transistor Q30 and the second gate electrode 105 that forms the MOS capacitor Q31 are connected through the conductor 107, while the first gate electrode 106 is electrically insulated from the semiconductor substrate 101, as well as from the N type impurity diffusion layers 108 and 109, by the first gate insulating film 104, and the second gate electrode 105 is electrically insulated from the N type well 102, as well as from the P type impurity diffusion layers 110 and 111, by the first gate insulating film 103, so that the first gate electrode 106 and the second gate electrode 105 (as well as the conductor 107 which electrically connects these) form a floating gate electrode FG (see FIG. 15B).
In a thus formed memory cell 100, it is assumed that a predetermined first positive voltage is applied to the N type impurity diffusion layer 108 through the contact C101, a ground voltage is applied to the N type impurity diffusion layer 109 through the contact C102, and a predetermined second positive voltage which is higher than the first positive voltage is applied to the P type impurity diffusion layer 110 and 111 and the N+ type impurity diffusion layer 112 through the contact C103 (hereinafter this state in which the voltages are applied is referred to as first voltage state). If the second positive voltage has a voltage value that is sufficiently high relative to the potential at which the second gate electrode 105 is charged, in other words, if the potential of the second gate electrode 105 is sufficiently low relative to the potential of the N type well 102 and the P type impurity diffusion layers 110 and 111, an inversion layer (hereinafter referred to as capacitor side inversion layer) is formed in the interface between the N type well 102 beneath the second gate electrode 105 and the second gate insulating film 103. At this time, holes that are minority carriers in the capacitor side inversion layer are supplied from the adjacent P type impurity diffusion layers 110 and 111, and therefore, the potential of the capacitor side inversion layer is coupled to the second positive voltage.
Incidentally, the capacitance between the capacitor side inversion layer and the second gate electrode 105 depends on the size and materials. Meanwhile, in the case where the potential of the first gate electrode is sufficiently high in the positive direction relative to the semiconductor substrate 101 in the portion where the first gate electrode 106 and the semiconductor substrate 101 overlap in the first gate electrode 106 that is electrically connected to the second gate electrode 105, an inversion layer (hereinafter referred to as transistor side inversion layer) is formed in the interface between the semiconductor substrate 101 located beneath the first gate electrode 106 and the first gate insulating film 104, and the capacitance between the transistor side inversion layer and the first gate electrode 106 depends on the size and materials.
In the case where the potential of the semiconductor substrate 101 is the ground potential in the above described first voltage state, there is a difference in potential that is the same as the second positive voltage between the semiconductor substrate 101 and the capacitor side inversion layer. The second gate electrode 105 and the first gate electrode 106 are electrically connected and at the same potential, and therefore, the second gate electrode 105 and the first gate electrode 106 (that is to say, the floating gate electrode FG) are at a predetermined positive potential that is determined by the capacitance vis-à-vis the capacitor side inversion layer, and the capacitance vis-à-vis the transistor side inversion layer (a higher potential).
At this time, the potential of the first gate electrode 106 is higher than the semiconductor substrate 101, and therefore, in the case where this difference in potential is sufficiently high, a transistor side inversion layer is formed in the interface between the portion where the first gate electrode 106 and the semiconductor substrate 101 overlap and the first gate insulating film 6, as described above. In the above described first voltage state, the first positive voltage is applied to the N type impurity diffusion layer 108 through the contact C101 and the ground voltage is applied to the N type impurity diffusion layer 109 through the contact C102, and thus, a positive electrical field is generated toward the N type impurity diffusion layer 108 from the N type impurity diffusion layer 109 and electrons within the N type impurity diffusion layer 109 accelerate under the influence of this positive electrical field so as to become of a hot electron state. These hot electrons are attracted to the first gate electrode 106 in a high voltage state and thus injected into the floating gate electrode FG. As a result, the floating gate electrode FG is charged negative.
In the MOS transistor Q30, the voltage value to be applied to the N type well 102 through the contact C103 for forming the transistor side inversion layer varies depending on the amount of electrons stored in the floating gate electrode FG. That is to say, in the case where a predetermined third positive voltage is applied through the contact C103 and a predetermined fourth positive voltage is applied to the N+ impurity diffusion layer 108 through the contact C101, if the MOS transistor Q30 becomes of a conductive state with a transistor side inversion layer present, this means that a sufficient amount of electrons are not stored in the floating gate electrode FG; conversely, if the MOS transistor Q30 is in a non-conductive state without there being a transistors side inversion layer, this means that a sufficient amount of electrons are stored in the floating gate electrode FG. Usually data is programmed, in the state where a sufficient amount of electrons are stored in the floating gate electrode FG, which is thus charged negative, and data is not programmed, in the other state.
That is to say, the above described fourth positive voltage is applied to the N type impurity diffusion layer 108 through the contact C101, the ground voltage is applied to the N type impurity diffusion layer 109 through the contact C102, and the above described third positive voltage is applied to all of the P type impurity diffusion layers 110 and 111 and the N+ type impurity diffusion layer 112 through the contact C103 (hereinafter this state in which the voltages are applied is referred to as second voltage state), so that it can be determined whether or not the current flowing through the bit line connected to the contact C101 or the current flowing through the source line connected to the contact C102 is detectable, and the results of the determination are matched with the two values: “0” and “1,” and thus, a readout process for two-value data stored in the memory cell 100 is carried out.
Thus, the memory cell 100 becomes of the above described first voltage state so that a data programming process is carried out, and becomes of the above described second voltage state so that a data readout process is carried out. Here, the floating gate electrode FG, which is charged negative when hot electrons are injected through the programming process, is peripherally isolated by the insulating film (the first gate insulating film 103 and the second gate insulating film 104), and therefore the charge is not volatile, so that the structure makes it possible to maintain the charged state for a long period of time. In addition, a programming process or readout process is selected for a memory cell 100, depending on the voltage applied through the contact C103, and therefore, the P type impurity diffusion layers 110 and 111 and the N+ type impurity diffusion layer 112, to which a voltage is applied through the contact C103 in the memory cell 100, correspond to the control gate electrode CG in EEPROM cells with a floating gate structure.
Next, a case where the data stored in the memory cell 100 in a programmed state in which the floating gate electrode FG is charged negative is erased is described.
In the case of an erasing operation, a ground voltage is applied to the P type impurity diffusion layers 110 and 111 and the N+ type impurity diffusion layer 112 through the contact C103, so that a predetermined fifth positive voltage (approximately the same as the first positive voltage or higher) is applied to the N type impurity diffusion layer 108 through the contact C101, and the contact C102 becomes of a floating state (with a high impedance) (hereinafter this state in which the voltages are applied is referred to as “third voltage state”). At this time, there is a difference in potential between the floating gate electrode FG (first gate electrode 106) and the N type impurity diffusion layer 108, so that a strong electrical field is generated, and the electrons stored within the floating gate electrode FG are drawn out to the N type impurity diffusion layer 108 side as a result of the FN (Fowler-Nordheim) tunneling phenomenon, and the programming state changes. In this case, the above descried fifth positive voltage may be applied to the N type impurity diffusion layer 109 through the contact C102 as well, so that a strong electrical filed is generated from the floating gate electrode FG to the facing surface of the semiconductor substrate 101, and thus, electrons can be drawn out using this electrical field.
Non-Patent Document 1 discloses a method for injecting hot holes into the floating gate electrode FG as another erasing method. The erasing method disclosed in Non-Patent Document 1 can be applied in the memory cell 100 in FIG. 15 in the following manner. That is to say, a ground voltage or negative voltage is applied to the control gate electrode CG, and at the same time, a predetermined positive voltage is applied to the N type impurity diffusion layer 108 through the contact C101. At this time, there is a large difference in potential between the N type impurity diffusion layer 108 and the control gate electrode CG, which have opposite polarities, and as a result, the surface of the N type impurity diffusion layer 108 becomes of a deep depletion state, making the energy band curve steeply. At this time, electrons tunnel from a valence band to a conduction band through band-band tunneling. At this time, electrons-hole pairs are generated, and the electrons flow into and are absorbed by the N type impurity diffusion layer 108, while the generated holes accelerate in the horizontal direction as a result of the electrical field in the horizontal direction between the N type impurity diffusion layer 108 and the semiconductor substrate 101 (with the semiconductor substrate 101 at the ground potential) so as to become hot holes, which are attracted to the first gate electrode 106, which is in a positive voltage state, or close to the ground voltage, and as a result they are injected into the floating gate FG (band-band tunneling induced hot hole injection). The injected hot holes offset electrons stored within the floating gate electrode FG so as to change the negatively charged state, and thus information is erased.
Here, though the method for applying a voltage is similar between the above described erasing method using the FN tunneling phenomenon and the erasing method using hot hole injection, the two are different in that it is essential that an ultra-thin gate insulating film be used in order to enhance the internal electrical field in the insulating film enough to cause the tunneling phenomenon when the voltage is within a practical range according to the former, while it is not necessary to use an ultra-thin gate insulating film according to the latter.
In addition to nonvolatile semiconductor memory devices that can be mounted on a substrate during a standard CMOS process, a DRAM (volatile semiconductor memory device) where data can be electrically written, which can be mounted on a substrate without adding any new steps to the standard CMOS process, is disclosed in the following Patent Document 4. The structure of the DRAM disclosed in Patent Document 4 is described below in reference to FIG. 16. FIG. 16A is a schematic cross sectional diagram showing the memory cell 200 used in the DRAM disclosed in Patent Document 4, and FIG. 16B is an equivalent circuit diagram showing a memory cell array.
The memory cell 200 is formed of an N channel type MIS transistor having an SOI structure (insulating gate type field effect transistor). That is to say, an SOI substrate where a silicon oxide film 202 is formed on a silicon substrate 201 as an insulating film and a P type silicon layer 203 is formed on the silicon oxide film 202 is used for the memory cell 200. A gate electrode 205 is formed through a gate oxide film 204 over the P type silicon layer 203 in the SOI substrate, and n type source and drain diffusion layers 206 and 207 are self-aligned with the gate electrode 205.
A number of memory cells 200 are aligned in rows and columns, so that a memory cell array where the gates 205 of the memory cells 200 aligned in rows are connected to word lines WL, the drains 207 of the memory cells 200 aligned in columns are connected to bit lines BL, and the sources 206 of the memory cells 200 are connected to ground lines is formed. In each memory cell 200, a first data state in which a first threshold voltage is provided when excessive majority carriers are stored in the P type silicon layer 203, and a second data state in which a second threshold voltage is provided when the excessive majority carriers are released from the P type silicon layer 203 are held dynamically, and data can be written in any bit unit, and furthermore, an initialization mode where all of the memory cells 200 in the memory cell array are programmed into in the first data state is provided.
The n type source and drain diffusion layers 206 and 207 are formed so deep as to hit the silicon oxide film 202 below. Accordingly, the body region made of the P type silicon layer 203 is isolated from the sides and bottom so as to become of a floating state.
The principle behind how a DRAM made up of N channel type MIS transistors operates is explained below. Storage of holes, which are majority carriers in the body region of the MIS transistors, is used to store data. That is to say, the MIS transistors operate in a pentode region, so that impact ions are generated in the vicinity of the drain 207. Holes which are excessive majority carriers generated through impact ionization are held in the P type silicon layer 203, and the state in which holes are stored corresponds to data “1,” for example. The PN junction between the drain diffusion layer 207 and the P type silicon layer 203 can be biased in the forward direction so that excessive holes in the P type silicon layer 203 are released to the drain side, of which the state corresponds to data “0.”
The data “0” or “1” is stored as a difference in the state of holes stored within the body region (that is to say, the difference in potential) and as a difference in the threshold voltage of the MIS transistor. That is to say, the threshold voltage Vth1 in the data “1” state, in which the potential in the body region is high due to holes being stored, is lower than the threshold voltage Vth0 in the data “0” state. In order to hold the data “1” state, in which holes which are majority carriers are stored in the body region, it is necessary to apply a negative voltage to the word line. This state in which data is stored does not change, even when a readout operation is carried out, unless an operation for writing in the opposite data (an erasing operation) is carried out. That is to say, nondestructive readout is possible.
Data readout methods include methods for detecting difference in the current for driving a memory cell having two storage states by applying a voltage between the threshold voltage Vth0 and Vth1 in the above described two storage states or a voltage that is not lower than the two threshold voltages to the word line. Methods for detecting difference in the current for driving include methods for driving a word line after pre-charging a bit line to a predetermined potential and checking the fall in the potential of the bit line at that time, methods for increasing the potential of a bit line after pre-charging a word line and checking the rate of increase in the potential of the bit line, and methods for increasing the potential of a word line after the potential of a bit line is clamped to a predetermined potential and checking the difference in the bit line current between memory cells in different states.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 3-12097
Patent Document 2: U.S. Pat. No. 5,065,362
Patent Document 3: Japanese Unexamined Patent Application Publication No. 6-334190
Patent Document 4: Japanese Unexamined Patent Application Publication 2002-260381
Non-Patent Document 1: Boaz Eitan et al., “Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a real Challenge to Floating Gate Cells?” Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, p. 522-523